RISC V is open source RISC ( Reduced Instruction Set Computing ) instruction code which can be modified freely and used to try out new Ideas. So far the idea of modification and actually building something out of it was a expensive preposition until SiFive announced its plan to build processors based on RISC V.
SiFive, founded by the creator of RISC-V , is the first fabless semiconductor company offering to build customized silicon based on the free and open RISC-V instruction set architecture. With RISK V & SiFive collaboration new changes can be made and implemented to test new ideas at a very less cost and being open source ideas can be shared and modified for individual
Here is a brief summary of CISC & RISC architectures to get an idea about their differences
CISC Architecture – can understand the operations in very few lines due to built in features of processor hardware. Well known and perhaps the only one CISC processor around is Intel’s x86
RISC Architecture – can execute simple instruction in one clock cycle. many lines are needs to execute a function but each is completed in one clock cycle and ultimately the operation takes almost same clock cycles as CISC operation. As hardware is not needed to implement complex logic the capacity can be used to create more general purpose registers.
So far these instruction sets are managed by big chip manufacturers and it is very difficult and costly to modify owning to huge development and research costs by companies . With the advent of SiFive the scenario of custom processor manufacturing is going to change , though it will not be free but it will be at a much reduced & affordable cost to experiment and explore .